In this module we will study automatic test pattern generation (ATPG) using sensitization–propagation -justification approach. We will first introduce the basics of. 1. VLSI Design Verification and Testing. Combinational ATPG Basics. Mohammad Tehranipoor. Electrical and Computer Engineering. University of Connecticut. Boolean level. • Classical ATPG algorithms reach their limits. ➢ There is a need for more efficient ATPG tools! 6. Circuits. • Basic gates. – AND, OR, EXOR, NOT.
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As design trends move toward nanometer technology, new manufacture testing problems are emerging.
Fault activation establishes a signal value at the fault model site that is opposite of the value produced by the fault model. If one driver dominates the other driver in a bridging situation, the dominant driver forces the logic to the other atpv, in such case a dominant bridging fault is used.
Bridging to VDD or Vss is equivalent to stuck at fault model. In such a circuit, any single fault will be inherently undetectable. Fault propagation moves the resulting signal value, or fault effect, forward by sensitizing a path from the fault site to a primary output.
Hence, if a circuit has n signal lines, there are potentially 2n stuck-at faults defined on the circuit, of which some can be viewed as being equivalent to others.
These metrics generally indicate test quality higher with more fault detections and test application time higher with more patterns. The combinational ATPG method allows testing the individual nodes or flip-flops of the logic circuit without being concerned with the operation of the overall circuit. ATPG is a topic that is covered by several conferences throughout the year.
Combinational ATPG Basics
Various search strategies and heuristics have been devised to find a shorter sequence, or to find a sequence faster. Equivalent faults produce the same faulty behavior for all input patterns. A short circuit between two signal lines is called bridging faults. The logic values observed at the device’s primary outputs, while applying a test pattern to some device under test Basivsare called the output of that test pattern.
Second, it is possible that a detection pattern exists, but the algorithm cannot find one. Historically, ATPG has focused on a set of faults derived from a gate-level fault model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. It is also called a permanent fault model because the faulty effect is assumed to be permanent, in contrast to intermittent faults which occur seemingly at random and transient faults which occur sporadically, perhaps depending on operating conditions e.
This allows using a relatively simple vector matrix to quickly test all the comprising FFs, as well as to trace failures to specific FFs.
Therefore, many different ATPG methods have been developed to address combinational and sequential circuits. Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational logic circuit. A fault is said to be detected by a test pattern if the output of that test pattern, when testing a device that has only that one fault, is different than the expected output.
Retrieved from ” https: Sequential-circuit ATPG searches for a sequence of test vectors to detect a particular fault through the space of all possible test vector sequences.
From Wikipedia, the free encyclopedia. Any single fault from the set of equivalent faults can represent the whole set. For designs that are sensitive to area aypg performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG.
Automatic test pattern generation – Wikipedia
This page was last edited on 23 Novemberat The effectiveness of ATPG is measured by the number of baeics defects, or fault modelsdetectable and by the number of generated patterns. The classic example of this is a redundant circuit, designed such that no single fault causes the output to change. During test, a so-called scan-mode bbasics enabled forcing all flip-flops FFs to be connected in a simplified fashion, effectively bypassing their bascis as intended during normal operation.
At transistor level, a transistor maybe stuck-short or stuck-open.
NPTEL :: Computer Science and Engineering – VLSI Design Verification and Test
For nanometer technology, many current design validation problems are becoming manufacturing test problems as well, so new fault-modeling and ATPG techniques will be needed.
However, according to reported results, no single strategy or heuristic out-performs others for all applications or circuits. First, the fault may be intrinsically undetectable, such that no patterns exist that can detect that particular fault. The generated patterns are used to test semiconductor devices after manufacture, or to assist with determining the cause of failure failure analysis .
ATPG can fail to find a test for a particular fault in at least two cases. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition.
In stuck-short, a transistor behaves as it is always conducts or stuck-onand stuck-open is when a transistor never conducts current or stuck-off.